W65C832_1 Datasheet, PDF (20/64 Pages) –

WDC
THE WESTERN DESIGN CENTER, INC.
W65CS32
2.5 Emulation Status (ES/E16)
The Emulation Status output ES/E16 reflects the state of the Emulation ES and E16
mode flags in the Processor Status (P) Register. This signal may be thought of as
an opcode extension and used for memory and system management.
2.6 Interrupt Request (IRQ-)
The Interrupt Request input signal is used to request that an interrupt sequence be
initiated. When the IRQ Disable (I) flag is cleared, a low- input logic level
initiates an interrupt sequence after the current instruction is completed. The
Wait-for-Interrupt (WAI) instruction may be executed to ensure the interrupt will be
recognized immediately. The Interrupt Request vector address is OOFFFE,F (Emulation
mode) or OOFFEE, F (Native mode). Since IRQ- is a level-sensitive input, an
interrupt will occur if the interrupt source was not cleared since the last
interrupt. Also, no interrupt will occur if the interrupt source is cleared prior
to interrupt recognition.
2.7 Memory Lock (ML-)
The Memory Lock output may be used to ensure the integrity of Read-Modify-Write
instructions in a multiprocessor system. Memory Lock indicates the need to defer
arbitration of the next bus cycle. Memory Lock is low during the last three, five
or nine cycles of ASL, DEC, INC, LSR, ROL, ROR, TRB, and TSB memory referencing
instructions, depending on the state of the M and ES flags.
2.S Memory/Index Select Status (M/X)
This multiplexed output reflects the state of the AcctJInu-lator (M) and Index (X)
select flags (bits 5 and 4 of the Processor Status (P) Register. Flag M is valid
during the Phase 2 clock negative transition and Flag X is valid during the Phase 2
clock positive transition. These bits may be thought of as opcode extensions and
may be used for memory and system management.
2.9 Non-Maskable Interrupt (NMI-)
A negative transition on the NMI- input initiates an interrupt sequence. A
high-to-Iow transition initiates an interrupt sequence after the current instruction
is completed. The Wait for Interrupt (WAI) instruction may be executed to ensure
that the interrupt will be recognized immediately. The Non-Maskable Interrupt
vector address is OOFFFA,B (S-bit Emulation mode), OOFFEA,B (16-bit Emulation mode)
or OOFFDA,B (Native mode). Since NMI- is an edge-sensitive input, an interrupt will
occur if there is a negative transition while servicing a previous interrupt. Also,
no interrupt will occur if NMI- remains low.
2.10 phase 2 In (PHI2)
This is the system clock input to the microprocessor internal clock generator.
During the low power Standby Mode, PHI2 may held in the high or low state to
preserve the contents of internal registers. However, usually it is held in the
high state.
MARCH 1990
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