W65C832_1 Datasheet, PDF (10/64 Pages) –

WDC
THE WESTERN DESIGN CENTER, INC.
W65C832
SECTION 1
W65C832 FUNCTION DESCRIPTION
The W65C832 provides the design engineer with upward mobility and software
compatibility in applications where a 32-bit system configuration is desired. The
W65C832's 32-bit hardware configuration, coupled with current software allows a wide
selection of system applications. In the Emulation mode, the W65C832 offers many
advantages, including full software compatibility with 6502, W65C02 or W65C816
coding. In addition, the W65C832' s powerful instruction set and addressing modes
make it an excellent choice for new 32-bit designs.
Internal organization of the W65C832 can be divided into two parts: 1) The
Register Section and 2) The Control Section. Instructions (or opcodes) obtained
from program memory are executed by implementing a series of data transfers within
the Register Section. Signals that cause data transfers to be executed are
generated within the Control Section. The W65C832 has a 32-bit internal
architecture with an 8-bit external data bus.
1.1 Instruction Register and Decode
An opcode enters the processor on the Data Bus, and is latched into the Instruction
Register during the instruction fetch cycle. This instruction is then decoded,
along with timing and interrupt signals, to generate the various Instruction
Register control signals.
1.2 Timing Control Unit (TCU)
The Timing Control Unit keeps track of each instruction cycle as it is executed.
The TCU is set to zero each time an instruction fetch is executed, and is advanced
at the beginning of each cycle for as many cycles as is required to complete the
instruction. Each data transfer between registers depends upon decoding the
contents of both the Instruction Register and the Timing Control Unit.
1.3 Arithmetic and Logic Unit (ALU)
All arithmetic and logic operations take place within the 32-bit ALU. In addition
to data operations, the ALU also calculates the effective address for relative and
indexed addressing modes. The result of a data operation is stored in either memory
or an internal register. Carry, Negative, OVerflow and Zero flags may be updated
following the ALU data operation.
1.4 Internal Registers (Refer to Programming Model)
MARCH 1990
2