W65C832_1 Datasheet, PDF (11/64 Pages) –

WOC
THE WESTERN DESIGN CENTER, INC.
W65C832
1.5 Accumulator
The Accumulator is a general purpose register which stores one of the operands, or
the result of most arithmetic and logical operations. In the Native mode the
Accumulator can be 8-, 16- or 32-bits wide.
1.6 Data Bank Register (DBR)
During modes of operation, the 8-bit Data Bank Register holds the default bank
address for memory transfers. The 24-bit address is composed of the 16-bit
instruction effective address and the 8-bit Data Bank address. The register value
is multiplexed with the data value and is present on the Data/Address lines during
the first half of a data transfer memory cycle for the W65C832. The Data Bank
Register is initialized to zero during Reset.
1.7 . Direct (D)
The 16-bit Direct Register provides an address offset for all instructions using
direct addressing. The effective bank zero address is formed by adding the 8-bit
instruction operand address to the Direct Register. The Direct Register is
initialized to zero during Reset.
1.8 Index (X and Y)
There are two Index Registers (X and Y) which may be used as general purpose
registers or to provide an index value for calculation of the effective address.
When executing an instruction with indexed addressing, the microprocessor fetches
the opcode and the base address, and then modifies the address by adding the Index
Register contents to the address prior to performing the desired operation.
Pre-indexing or post-indexing of indirect addresses may be selected. In the Native
mode, both Index Registers are 32 bits wide (providing the Index Select Bit (X)
equals zero). If the Index Select Bit (X) equals one, both registers will be 8 bits
wide, and the high bytes if forced to zero.
1.9 Processor Status (P)
The 8-bit Processor Status Register contains status flags and mode select bits. The
Carry (C), Negative (N), Overflow (V), and Zero (Z) status flags serve to report the
status of most ALU operations. These status flags are tested by use of Conditional
Branch instructions. The Decimal (D), IRQ Disable (I), Memory/Accumulator (M), and
Index (X) bits are used as mode select flags. These flags are set by the program to
change microprocessor operations.
The Emulation (E8 and E16) select and the Break (B) flags are accessible only
through the Processor Status Register. The Emulation (E8) mode select flag is
selected by the Exchange Carry and Emulation Bits (XCE) instruction. The XFE
instruction exchanges the Emulation (E8 and E16) mode select flags with the Overflow
and Carry Flags. Table 1, Emulation and Register Width Control, illustrates the
features of the Native and Emulation modes. The M and X flags are always equal to
one in the 8-bit Emulation mode. When an interrupt occurs during the Emulation
mode, the Break flag is written to stack memory as bit 4 of the Processor Status
Register.
MARCH 1990
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