W65C832_1 Datasheet, PDF (21/64 Pages) –

WDC
THE WESTERN DESIGN CENTER, INC.
W65C832
2.11 Read/Write (R/W-)
When the R/W- output signal is in the high state, the microprocessor is reading data
from memory or I/O. When in the low state, the Data Bus contains valid data from
the microprocessor which is to be stored at the addressed memory location. The R/W­
signal may be set to the high impedance state by Bus Enable (BE).
2.12 Ready (RDY)
This bidirectional signal indicates that a Wait for Interrupt (WAI) instruction has
been executed allowing the user to halt operation of the microprocessor. A low
input logic level will halt the microprocessor in its current state. Returning RDY
to the active high state allows the microprocessor to continue following the next
PHI2 Clock negative transition. The RDY signal is internally pulled low following
the execution of a Wait for Interrupt (WAI) instruction, and then returned to the
high state when a RES-, ABORT-I NMI- ₁ or IRQ- external interrupt is provided. This
feature may be used to eliminate interrupt latency by placing the WAI instruction at
the beginning of the IRQ- servicing routine. If the IRQ- Disable flag has been set _l
the next instruction will be executed when the IRQ- occurs. The processor will not
stop after a WAI instruction if RDY has been forced to a high state. However I this
feature should only be used on ASIC's and the RDY buffer modified. The Stop (STP)
instruction has no effect on RDY.
2.13 Reset (RES-)
The Reset input is used to initialize the microprocessor and start program
execution. The Reset input buffer has hysteresis such that a simple R-C timing
circuit may be used with the internal pullup device. The RES- signal must be held
low for at least two clock cycles after VDD reaches operating voltage. Ready (RDY)
has no effect while RES- is being held low. During the Reset conditioning period _l
the following periodl the following processor initialization takes place:
D
0000
DBR ₌ 00
PBR
00
Registers
SH = 01
XH = 00
YH
00
N V/E16 M X D I z C/E8
P
=
I
* ^{*/1 1 1 o 1} * ^*/1
I*
_______________________________________ 1
not
initialized
STP and WAI instructions are cleared.
E8
E16
M/X
R/W-
SYNC
=1
=1
=1
1
=⁰
Signals
VDA = 0
VP-
1
VPA = 0
When Reset is brought highl an interrupt sequence is initiated:
o R/W- remains in the high state during the stack address cycles.
o The Reset vector address is OOFFFC/D.
MARCH 1990
13