W65C832_1 Datasheet, PDF (63/64 Pages) –

WDC
THE WESTERN DESIGN~CENTER, INC.
W65C832,
8.12 How Hardware Interrupts, BRK, and COP Instructions Affect the Program Bank and
the Data Bank Registers
8.12.1 When in the Native mode, the Program Bank register (PBR) is cleared to
00 when a hardware interrupt, BRK or COP is executed. Ift' the· Native
mode, previous PBR contents is automatically saved on Stack.
8.12.2 In the Emulation mode, the PBR and DBR registers are cleared to OO.when i?
a hardware interrupt, BRK or COP is executed. In this case, previous
contents of the PBR are not automatically saved.
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8.12.3 Note that a Ret urn from .,Interrupt (RTI) should always be executed' '~·from
the same "mode" which originally ~gEm'erated the interrupt~
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8.13 Binary Mode
The Binary Mode is set whenever a :tta:tdwitre"'r~,softwate,14..nte~rupt:r-:j,s,)':zexeGuted.· 8
The D flag within the Status Register is cleared to zero.
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8.14 WAI Instruction
The WAI instruction pulls RDY low and 'places the p~ocessor· ,in' -the WAI "low
power" mode. NMI-, IRQ- or RESET will termina'te the' WAI~.conditiotr alld transfer
control to the interrupt handler routine: Note that an ABORT~ input will abort
the WAI instruction, but will not restart the;· processor. When;':·the. tStatus
Register I flag is set (IRQ- disabled), the IRQ.:- interrupt will ca1fie the next
te ^{instruction (following the WAI instruction) to be executed without going to the}
IRQ- interrupt handler. This method results in the highest' speedtespense~: an
IRQ- input. When an interrupt is received after an ABORT- whic~ocaurs during
the WAI instruction, the processor will return to the 'WAI instruction. Other
than RES- (highest priority), ABORT- is the next highest priority, ~followed by ,
NMI- or IRQ- interrupts.
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8.15 The STP instruction disables the PHI2 clock to all circuitry. When disabled,
the PHI2 clock is held in the high state. In this case, the Dta Bus will
remain in the data transfer state and the Bank address will notb~ multiplexed
onto the Data Bus. Upon executing the STP instruction, the RES- signal is the
only input which can restart the processor. The processor 'is . r-e'started 'by t
enabling the PHI2 clock, which occurs on the falling edge of the RES- input.
Note that the external oscillator must be--stable, and ,operating p'roperly before
RES- goes high.
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8.16 COP Signatures
':" '.,
Signatures 00-7F may be user defined, while signatures 80-FF are reserved for
instructions on future microprocessors:~ ::,c:contact WDC for software-·emulation of
future microprocessor hardware functio{ls ~, .,[
8.17 WDM Opcode Use
The WDM opcode will be used on future microprocessors.
MARCH 1990
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