W65C832_1 Datasheet, PDF (52/64 Pages) –

WDC
THE WESTERN DESIGN CENTER, INC.
W65C832
ADDRESS MODE
CYCLE VP,ML,VDA,VPA ADDRESS BUS
*24b.Block Move Negative
I^- l. 1 ¹ 1 ¹ PBR,PC
(backward)-xyc
(18) I 2. 1 1 0 1 PBR,PC+1
(MVN)
(1S) I 3. 1 1 0 1 PBR,PC+2
(lOp Code)
N-21 4. 1 1 1 0 SBA,X
(3 bytes)
Bytel 5. 1 1 1 0 DBA,Y
(7 cycles)
C=21 6. 1 1 0 0 DBA,Y
I ^7. 1 ¹ 0 0 ^DBA,Y
x=Source Address
y=Destination
I
1 1 1 1 PBR,PC
c=tof bytes to move-l(18) I 2. 1 1 0 1 PBR,PC+l
x,y Increment
(18) I 3. 1 1 0 1 PBR,PC+2
MVN is used when the N-ll 4. 1 1 1 0 SBA,X+l
dest. start address Bytel 5. 1 1 1 0 DBA, Y+l
is lower (more
C=ll 6. 1 1 0 0 DBA,Y+l
negative) than the source I 7. 1 1 0 0 DBA,Y+l
start address.
-_{I l. 1 1 1 1 PBR,PC}
FFFFF
(18) I 2. 1 1 0 1 PBR,PC+l
I
Source End (18) I 3. 1 1 0 1 PBR,PC+2
II
N Bytel 4. 1 1 1 0 SBA,X+2
I
1
I^{-1I -DSoeustr.cEendStart}
C=OI 5. 1 1
I 6. ^{1 1}
1
0
0 DBA,Y+2
0 DBA,Y+2
V _I -Dest.Start
I ^{7. 1 1} 0 ^{0 DBA,Y+2}
000000
I l. ^{1 1 1 1 PBR,PC+3}
DATA BUS R!W
OpCode 1
DBA
1
SBA
1
SRC Data 1
DEST Data 0
IO
1
IO
1
OpCode
1
DBA
1
SBA
1
SRC Data 1
DEST Data 0
IO
1
IO
1
OpCode 1
DBA
1
SBA
1
SRC Data 1
DEST Data 0
IO
1
IO
1
New OpCode 1
1. Add 1 byte (for immediate only) for 16-bit data, add 3 bytes for 32-bit data,
add 1 cycle for 16-bit data and 3 cycles for 32-bit data.
2. Add 1 cycle for direct register low (DL) not equal O.
3. Special case for aborting instruction. This is the last cycle which may be
aborted or the Status, PBR or DBR registers will be updated.
4. Add 1 cycle for indexing across page boundaries, or write, or 16-bit or 32-bit
Index Registers. When 8-bit Index Registers or in the emulation mode, this
cycle contains invalid addresses.
5. Add 1 cycle if branch is taken.
6. Add 1 cycle if branch is taken across page boundaries in 6502 emulation mode.
7. Subtract 1 cycle for 6502 emulation mode.
8. Add 1 cycle for REP, SEP.
9. Wait at cycle 2 for 2 cycles after NMI- or IRQ- active input.
10. R/W- remains high during Reset.
11. BRK bit 4 equals "0" in Emulation mode.
12. PHP and PLP.
13. Some OpCodes shown are not on the W65C02.
14. VDA and VPA are not valid outputs on the W65C02 but are valid on the W65C832.
The two signals, VDA and VPA, are included to point out the upward
compatibility to the W65C832. When VDA and VPA are both a one level, this is
equivalent to SYNC being a one level.
15. The PBR is not on the W65C02.
16. Co-processors may monitor the signature byte to aid in processor to
co-processor communications.
17. Add 1 cycle for 32-bit Index Register mode.
18. Subtract 2 bytes and 2 cycles when in W65C832 Native mode for MVN and MVP.
MARCH 1990
41