W65C832_1 Datasheet, PDF (25/64 Pages) –

VIDC
THE WESTERN DESIGN CENTERI INC.
W65C832
* 3.5.7 Direct Indirect Indexed-(d)/Y
This address mode is often referred to as IndirectlY' The second byte
of the instruction is added to the Direct Register (D). The 16-bit
contents of this memory location is then combined with the Data Bank
register to form a 24-bit base address. The Y Index Register is added
to the base address to form the effective address. In native mode this
creates 32-bit effective addresses.
* 3.5.8
Instruction: opcode _I offset I
1 ^{Direct Register}
+
I offset
00 _I direct address
then:
1 00 1 (direct address)
+1 DBR 1
1
base address
Operand
+
1
I Y Reg
Address:
I effective address
Direct Indirect Long Indexed-[d]/Y
with this addressing model the 24-bit base address is pointed to by the
sum of the second byte of the instruction and the Direct Register. The
effective address is this 24-bit base address plus the Y Index Register.
In native mode this creates 32-bit effective addresses.
3.5.9
Instruction: oEcode ₁ offset ₁
1 ^{Direct Register}
+
I ^offset
00 I ^{. direct} address
then:
1
(direct address)
+1 DBR I
I
base address
Operand
+
I
1 Y Reg
Address:
1 effective address
Direct Indexed Indirect-(d,x)
This address mode is often referred to as Indirect, X. The second byte
of the instruction is added to the sum of the Direct Register and the X
Index Register. The result points to the low-order 16 bits of the
effective address. The Data Bank Register contains the high-order 8
bits of the effective address.
Instruction: oEcode 1 offset ₁
I ^{Direct Register}
+
I offset
I ^direct address
+1
1 X Reg
00 _I address
then:
1 00 1 (address)
Operand
+1 DBR 1
Address:
I effective address
MARCH 1990
17