W65C832_1 Datasheet, PDF (29/64 Pages) –

WDC
THE WESTERN DESIGN CENTER, INC.
W65C832
3.5.24 Block Source Bank, Destination Bank-xya
This addressing mode is used by the Block Move instructions. The second
byte of the instruction contains the high-order 8 bits of the
destination address. The Y Index Register contains the low-order 16
bits of the destination address. The third byte of the instruction
contains the high-order 8 bits of the source address. The X Index
Register contains the low-order bits of the source address. The
Accumulator contains one less than the number of bytes to move. When
the Accumulator is zero it will move one byte. The second byte of the
block move instructions is also loaded into the Data Bank Register. In
W65C832 native mode this X Index Register contains the entire source
address and the X Index Register contains the entire destination
address; therefore, the instruction is shorter by two bytes and two
cycles per byte moved.
Instruction: I opcode dstbnk I srcbnk I
Source
dstbnk -> DBR
Address:
srcbnk I
X Reg
Destination
DBR I
Y Reg
Address:
Increment (MVN) or decrement (MVP) X and Y.
Decrement C (if greater than zero), then PC+3->PC.
* In W65C832 native mode these addressing modes creates 32-bit effective data
space addresses.
MARCH 1990
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