W65C832_1 Datasheet, PDF (62/64 Pages) –

WDG
THE WESTERN DESIGN CENTER, INC.
W65C832
8.7 DBIBA Qperation when ROy is Pulled Low
When RDY is low, the Data Bus is held in the data transfer state (i.e., PHI2
high) .'rhe Bank address external transparent latch should be latched when the
. PHI2clo.ek or RDY is .low.
8!.%' M(X Output:·.
:..:1.:) ·~"'.S. ',.:
The MIX output reflects the valid of theM and X bits of the processor Status
iL ·~:Re,giS.ter{. ·The REP, SEP and PLP .instructions may change the state of the M and
X bits. Note that the NIX output is :invalid. during the instruction cycle
following REP, SEP and PLP instruction execution. This cycle is used as the
opcode fetch cycle of the next instruction.
::::: s:-: ,:":'; ,'J::7"',~ .::.. . :
- ,:.:; ':'
8.9.1 It should be noted that all opcodes function in all modes of operation.
However, some instructions and addressing modes are intended for W65C832
24-bit addressing and are therefore less useful for the W65C832. The
KG';: F .• .;,; i:oUQwing is a;; list of instructions and addressing modes which are
,!9:;8r.:'.~::..:; ~:t"t.marily intended for .W·65C832 use:
j:::od.e ~_ " .!.J JSL;RTL; Cd] i Cd] ,YiJMP aliJMLial,al,x
8L'j.r·.a;~9 .:?-.:Th~:o following .instru~tions may be used with the W65C832 even though a
JX91! 5::~ ~·~nck AO,dress is not multiplexed on the Data Bus:
9dj ~~ r~L~' :.PHKiPHB;PLB
.
:-;f. ~:t9;.~,.l'Deot'01lowing instructions have "limited" use in the Emulation mode:
... ~ "..... ;.8: 9.3 .. 1 The REP and SEP instructions cannot modify the M and X bits when
""~:',l ... in Jpe Emulation mode. In this mode the M and X bits will always be high
.~ .•• •..J. ;_~ ~ :~log~c 1).
8.9.3.2 When in the Emulation mode, the MVP and MVN instructions use the
~' . -~.:.
X and Y Index Registers for the memory address. Also, the MVP and MVN
illstructions can only move data within the memory range 0000 (Source
Bank) to OOFF (Destination Bank) for the W65C832, and 0000 to OOFF for
the ~W65C832.
.
­
8 ..19~n~lir~.9t . J~ps
:..,Â¥he JMP (a) ,and JML .(a) instructions use the direct Bank for indirect
addressing, while JMP (a, x) and JSR (a, x) use the Program Bank for indirect
address tables.
8.11 Switching Modes
-
1..:_ '
.. WhE;n switching from the Native mode to the Emulation mode, the X and M bits of
the Status Register are set high (logic 1), the high byte of the Stack is set
to 01, and the high bytes of the X and Y Index Registers are set to 00. To
save previous values, these bytes must always be stored before changing modes.
Note that the low byte of the S, X and Y Registers and the low and high byte of
the Accumulator (A and B) are not affected by a mode change.
MARCH 1990
49