W65C832_1 Datasheet, PDF (61/64 Pages) –

WOC
THE WESTERN DESIGN CENTER, INC.
W65C832
8.2.2
8.2.3
When in the Emulation mode and DH is not equal to zero, the direct
addressing range is OODHOO to OODHFF, except for [Direct] and [Direct],Y
addressing modes and the PEI instruction which will increment from
OODHFE or OODHFF into the next higher page.
When in the Emulation mode and DL in not equal to zero, the direct
addressing range is 000000 to OOFFFF.
8.3 Absolute Indexed Addressing
The Absolute Indexed addressing modes are used to address data outside the
direct addressing range. The W65C02 and W65C832 addressing range is OO(}:O to
FFFF. Indexing from page FFXX may result in a OOYY data fetch when using the
W65C02 or w65C832. In contrast, indexing from page ZZFFXX may result in
ZZ+l,OOYY when using the W65C832.
8.4 ABORT- Input
:- I
8.4.1
8.4.2
I
ABORT- should be held low for a period no~to exceed one cyp1e!; "AlsoI
if ABORT- is held low during the Abort Interrupt sequencer: the Abort
Interrupt will be aborted. It is not recommended to. abort.:;the:_~bort
Interrupt. The ABORT- internal latch is cleared during the sel?9~d cycle
of the Abort Interrupt. Asserting the ABORT- input after ~1!e ·~ollqwing
instruction cycles will cause registers to be modified:
.
8.4.1.1 Read-Modify-Write: Processor status modified if ABORTT is
asserted after a modify cycle.
.
8.4.1.2 RTI: Processor status modified if ABORT- is asserted"after
cycle 3.
8.4.1.3 IRQ-, NMI -, ABORT- BRRI COP: When ABORT- is asserted' after
cycle 2, PBR and DBR will become 00 (Emulation mode) or PBRwill become
00 (Native mode).
The Abort- Interrupt has been designed for virtual memory systems. For
this reason_l asynchronous ABORT/s- may cause undesirable results due to
the above conditions.
8.5 VDA and VPA Valid Memory Address Output Signals
When VDA or VPA are high and during all write cycles, the Address Bus is always
valid. VDA and VPA should be used to qualify all memory cycles. Note that
when VDA and VPA are both low _l invalid addresses may be generated. The Page
and Bank addresses could also be invalid. This will be due to low byte
addition only. The cycle when only low byte addition occurs is an optional
cycle for instructions which read memory when the Index Register consists of 8
bits. This optional cycle becomes a standard cycle for the Store instruction,
all instructions using the 16-bit Index Register mode, and the
Read-Modify-Write instruction when using 8- or 16-bit Index Register modes.
8.6 Apple II, IIe_l IIc and II+ Disk Systems
VDA and VPA should not be used to qualify addresses during disk operation on
Apple systems. Consult your Apple representative for hardware/software
configurations.
MARCH 1990
48