W65C832_1 Datasheet, PDF (19/64 Pages) –

WDC
THE WESTERN DESIGN CENTER, INC.
W65C832
Table 2-1 Pin Function Table
Pin
AO-A15
ABORT-
BE
PHI2(IN)
DO/A16-D7/A23
E8/El6
IRQ-
ML-
M/X
NMI-
ROY
RES-
R/W-
VDA
VP-
VPA
VDD
VSS
Description
Address Bus
Abort Input
Bus Enable
Phase 2 In Clock
Data Bus/Address Bus
Emulation Select
Interrupt Request
Memory Lock
Mode Select (Pm or Px)
Non-Maskable Interrupt
Ready
Reset
Read/Write
Valid Data Address
Vector Pull
Valid Program Address
Positive Power Supply (+5 volts)
Internal Logic Ground
2.1 Abort (ABORT-)
The Abort input is used to abort instructions (usually due to an Address Bus
condition). A negative transition will inhibit modification of any internal
register during the current instruction. Upon completion of this instruction, an
interrupt sequence is initiated. The location of the aborted opcode is stored as
the return address in stack memory. The Abort vector address is 00FFF8,9 (Emulation
mode) or 00FFE8,9 (Native mode). Note that ABORT- is a pulse-sensitive signal;
i.e., an abort will occur whenever there is a negative pulse (or level) on the
ABORT- pin during a PHI2 clock.
2.2 Address Bus (AO-A15)
These sixteen output lines form the low 16 bits of the Address Bus for memory and
I/O exchange on the Data Bus. The address lines may be set to the high impedance
state by the Bus Enable (BE) signal.
2.3 Bus Enable (BE)
The Bus Enable input signal allows external control of the Address and Data Buffers,
as well as the R/W- signal. With Bus Enable high, the R/W- and Address Buffers are
active. The Data/Address Buffers are active during the first half of every cycle
and the second half of a write cycle. When BE is low, these buffers are disabled.
Bus Enable is an asynchronous signal.
2.4 Data/Address Bus (DO/A16-D7/A23)
These eight lines multiplex address bits Al6-A23 with the data value DO-D7. The
address is present during the first half of a memory cycle, and the data value is
read or written during the second half of the memory cycle. Four memory cycles are
required to transfer 32-bit values. These lines may be set to the high impedance
state by the Bus Enable (BE) signal.
MARCH 1990
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