W65C832_1 Datasheet, PDF (26/64 Pages) –

WOC
THE WESTERN DESIGN CENTER, INC.
W65C832
3.5.10 Direct Indexed With X-d,x
The second byte of the instruction is added to the sum of the Direct
Register and the X Index Register to form the 16-bit effective address.
The operand is always in Bank O.
Instruction: opcode 1 offset 1
1 Direct Register
+
1 offset
1 direct address
Operand
+1
1 X Reg 1
Address:
1 00 leffective address 1
3.5.11 Direct Indexed With Y-d,y
The second byte of the instruction is added to the sum of the Direct
Register and the Y Index Register to form the 16-bit effective address.
The operand is always in Bank O.
Instruction: opcode 1 offset I
I Direct Register
+
I offset
1 direct address
Operand
+1
1 Y Reg 1
Address:
1 00 leffective address 1
* 3.5.12 Absolute Indexed With X-a,x
The second and third bytes of the instruction are added to the X Index
Register to form the low-order 16-bits of the effective address. The
Data Bank Register contains the high-order 8 bits of the effective
address. In native mode this creates 32-bit effective addresses.
Instruction: opcode r addrl I addrh
DBR I addrh 1 addrl
Operand
+1
1 X Reg
Address:
1 effective address
* 3.5.13 Absolute Long Indexed With X-al,x
The second, third and fourth bytes of the instruction form a 24-bit base
address. The effective address is the sum of this 24-bit address and
the X Index Register. In native mode this creates 32-bit effective
addresses.
Instruction: opcode I addrl 1 addrh baddr 1
baddr 1 addrh I addrl
Operand
+I
I X Reg
Address:
1 effective address
* 3.5.14 Absolute Indexed With Y-a,y
The second and third bytes of the instruction are added to the Y Index
Register to form the low-order 16 bits of the effective address. The
Data Bank Register contains the high-order 8 bits of the effective
address. In native mode this creates 32-bit effective addresses.
Instruction:
Operand
Address:
opcode 1 addrl 1 addrh
DBR I addrh 1 addrl
+1
1 Y Reg
effective address
MARCH 1990
18