W65C832_1 Datasheet, PDF (24/64 Pages) –

WDC
THE WESTERN DESIGN CENTER, INC.
W65C832
The following addressing mode descriptions provide additional detail as to how
effective addresses are calculated.
Twenty-four addressing modes are available for the W65C832. The 32-bit indexed
addressing modes are used with the W65C832i however, the high byte of the address is
not available to the hardware on the standard W65C832 but is available on the core
for ASIC's. Detailed descriptions of the 24 addressing modes are as follows:
3.5.1
3.5.2
Immediate Addressing-f
The operand is the second byte in 8-bit mode, second and third bytes
when in the 16-bit mode, or 2nd thru 5th bytes in 32-bit mode of the
instruction.
Absolute-a
With Absolute addressing the second and third bytes of the instruction
form the low-order 16 bits of the effective address. The Data Bank
Register contains the high-order 8 bits of the operand address.
Instruction:
Operand
Address:
3.5.3 Absolute 1ong-al
opcode addrl addrh
DBR addrh addrl
3.5.4
Instruction: opcode addrl addrh baddr I
Operand
Address:
baddr addrh addrl
Direct-d
The second byte of the instruction is added to the Direct Register (D)
to form the effective address. An additional cycle is required when the
Direct Register is not page aligned (01 not equal 0). The Bank register
is always O.
3.5.5
3.5.6
Instruction: opcode I offset I
I Direct Register
Operand
+
I offset I
Address:
00 leffective address I
Accumulator-A
This form of addressing always uses a single byte instruction. The
operand is the Accumulator.
Implied-i
Implied addressing uses a single byte instruction. The operand is
implicitly defined by the instruction.
MARCH 1990
16