W65C832_1 Datasheet, PDF (64/64 Pages) –

WDC
THE WESTERN DESIGN CENTER, INC.
W65C832
S.18 ROY Pulled During Write
The NMOS 6502 does not stop during a write operation. In contrast, both the
W65C02 and the W65C832 do stop during write operations. The W65C832 stops
during a write when in the Native mode, but does not stop when in the Emulation
mode.
8.19 MVN and MVP Affects on the Data Bank Register
The MVN and MVP instructions change the Data Bank Register to the value of the
second byte of the instruction (destination bank address) .
8.20 Interrupt Priorities
The following interrupt priorities will be in effect should more than one
interrupt occur at the same time:
RES­
ABORT ­
NMI ­
IRQ-
Highest Priority
Lowest Priority
8.21 Transfers from differing register sizes
All transfers from one register to another will result in a full 32-bit output
from the source register. The destinat·ion register size will determine the
number of bits actually stored in the destination register and the values
stored in the processor Status Register. The following are always 16-bit
transfers, regardless of the accumulator size:
TASiTSAiTADiTDA
8.22 Stack Transfers
When in the W65C02 Emulation mode, a 01 is forced into the high byte of the
16-bit stack pointer. When in the Native mode or W65C816 Emulation mode, the A
Accumulator is transferred to the 16-bit stack pointer. Note that in both the
Emulation and Native modes, the full 16 bits of the Stack Register are
transferred to the A Accumulator regardless of the state of the M bit in the
Status Register.
8.23 REP/SEP
WDC had problems using the REP and SEP instructions in early versions of the
high-speed W65C816 and W65CS02 devices and has been corrected on all W65CS32
devices.
MARCH 1990
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