MC9328MXS Datasheet, PDF (6/72 Pages) List of Unclassifed Manufacturers – Advance Information

Signals and Connections
Table 3. MC9328MXS Signal Descriptions (Continued)
Signal Name
Function/Notes
CAS
SDWE
SDRAM Column Address Select signal
SDRAM Write Enable signal
SDCKE0
SDCKE1
SDCLK
SDRAM Clock Enable 0
SDRAM Clock Enable 1
SDRAM Clock
RESET_SF
Not Used
Clocks and Resets
EXTAL16M
XTAL16M
EXTAL32K
Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when the internal oscillator circuit is
shut down.
Crystal output
32 kHz crystal input
XTAL32K
CLKO
RESET_IN
RESET_OUT
POR
32 kHz crystal output
Clock Out signal selected from internal clock signals.
Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all
modules (except the reset module and the clock control module) are reset.
Reset Out—Internal active low output signal from the Watchdog Timer module and is asserted from
the following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out.
Power On Reset—Internal active high Schmitt trigger input signal. The POR signal is normally
generated by an external RC circuit designed to detect a power-up event.
JTAG
TRST
TDO
Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.
Serial Output for test instructions and data. Changes on the falling edge of TCK.
TDI
TCK
TMS
Serial Input for test instructions and data. Sampled on the rising edge of TCK.
Test Clock to synchronize test logic and control register access through the JTAG port.
Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge
of TCK.
DMA
BIG_ENDIAN
Big Endian—Input signal that determines the configuration of the external chip-select space. If it is
driven logic-high at reset, the external chip-select space will be configured to little endian. If it is
driven logic-low at reset, the external chip-select space will be configured to big endian.
DMA_REQ
External DMA request pin.
ETM
ETMTRACESYNC
ETMTRACECLK
ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM mode.
ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM mode.
ETMPIPESTAT [2:0] ETM status signals which are multiplexed with A [22:20]. ETMPIPESTAT [2:0] are selected in ETM
mode.
ETMTRACEPKT [7:0] ETM packet signals which are multiplexed with ECB, LBA, BCLK(burst clock), PA17, A [19:16].
ETMTRACEPKT [7:0] are selected in ETM mode.
LCD Controller
LD [15:0]
LCD Data Bus—All LCD signals are driven low after reset and when LCD is off.
MC9328MXS Advance Information, Rev. 0
6
Freescale Semiconductor