MC9328MXS Datasheet, PDF (25/72 Pages) List of Unclassifed Manufacturers – Advance Information

3.9.2.7 WAIT Write Cycle without DMA
Address
1
CS5
2
EB
RW
3
programmable
min 0ns
programmable
min 0ns
Specifications
5
10
4
7
OE(logic ^high)
6
WAIT
11
9
DATABUS
(output to i.MX)
8
12
Figure 12. WAIT Write Cycle without DMA
Table 19. WAIT Write Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
Number
Characteristic
3.0 ± 0.3 V
Unit
Minimum
Maximum
1
CS5 assertion time
See note 2
–
ns
2
EB assertion time
See note 2
–
ns
3
CS5 pulse width
3T
–
ns
4
RW negated before CS5 is negated
2.5T-3.63
2.5T-1.16
ns
5
RW negated to Address inactive
64.22
–
ns
6
Wait asserted after CS5 asserted
–
1020T
ns
7
Wait asserted to RW negated
T+2.66
2T+7.96
ns
8
Data hold timing after RW negated
2T+0.03
–
ns
9
Data ready after CS5 is asserted
–
T
ns
10
EB negated after CS5 is negated
0.5T
0.5T+0.5
ns
11
Wait becomes low after CS5 asserted
0
1019T
ns
12
Wait pulse width
1T
1020T
ns
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
2. CS5 assertion can be controlled by CSA bits. EB assertion can also be programable by WEA bits in CS5L register.
3. Address becomes valid and RW asserts at the start of write access cycle.
4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor
25