MC9328MXS Datasheet, PDF (51/72 Pages) List of Unclassifed Manufacturers – Advance Information

Specifications
3.10 SPI Timing Diagrams
To use the internal transmit (TX) and receive (RX) data FIFOs when the SPI module is configured as a master, two
control signals are used for data transfer rate control: the SS signal (output) and the SPI_RDY signal (input). The
SPI1 Sample Period Control Register (PERIODREG1) can also be programmed to a fixed data transfer rate. When
the SPI module is configured as a slave, the user can configure the SPI1 Control Register (CONTROLREG1) to
match the external SPI master’s timing. In this configuration, SS becomes an input signal, and is used to latch data
into or load data out to the internal data shift registers, as well as to increment the data FIFO. Figure 38 through
Figure 42 show the timing relationship of the master SPI using different triggering mechanisms.
SS
1
SPIRDY
2
3
5
4
SCLK, MOSI, MISO
Figure 38. Master SPI Timing Diagram Using SPI_RDY Edge Trigger
SS
SPIRDY
SCLK, MOSI, MISO
Figure 39. Master SPI Timing Diagram Using SPI_RDY Level Trigger
SS (output)
SCLK, MOSI, MISO
Figure 40. Master SPI Timing Diagram Ignore SPI_RDY Level Trigger
SS (input)
SCLK, MOSI, MISO
Figure 41. Slave SPI Timing Diagram FIFO Advanced by BIT COUNT
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor
51