MC9328MXS Datasheet, PDF (56/72 Pages) List of Unclassifed Manufacturers – Advance Information

Specifications
3.13 SDRAM Controller
This section shows timing diagrams and parameters associated with the SDRAM (synchronous dynamic random
access memory) Controller.
SDCLK
CS
1
2
3S
3
3S
RAS
CAS
WE
3H
3S
3H
3H
3S
3H
ADDR
4S 4H
ROW/BA
COL/BA
DQ
DQM
8
3S
5
6
Data
7
3H
Note: CKE is high during the read/write cycle.
Figure 46. SDRAM Read Cycle Timing Diagram
Table 26. SDRAM Read Timing Parameter Table
Ref
No.
Parameter
1 SDRAM clock high-level width
2 SDRAM clock low-level width
3 SDRAM clock cycle time
3S CS, RAS, CAS, WE, DQM setup time
3H CS, RAS, CAS, WE, DQM hold time
1.8 ± 0.1 V
3.0 ± 0.3 V
Unit
Minimum Maximum Minimum Maximum
2.67
–
4
–
ns
6
–
4
–
ns
11.4
–
10
–
ns
3.42
–
3
–
ns
2.28
–
2
–
ns
MC9328MXS Advance Information, Rev. 0
56
Freescale Semiconductor