MC9328MXS Datasheet, PDF (21/72 Pages) List of Unclassifed Manufacturers – Advance Information

3.9.2.3 DTACK Write Cycle without DMA
Address
1
3
programmable
CS5
min 0ns
2
programmable
EB
min 0ns
RW
7
Specifications
5
10
4
OE ^{(logic high)}
6
DTACK
9
Databus
(input to i.MX)
8
11
Figure 8. DTACK Write Cycle without DMA
Table 15. Write Cycle without DMA: WSC = 111111, DTACK_SEL=0, HCLK=96MHz
Number
Characteristic
3.0 ± 0.3 V
Unit
Minimum
Maximum
1
CS5 assertion time
See note 3
–
ns
2
EB assertion time
See note 3
–
ns
3
CS5 pulse width
3T
–
ns
4
RW negated before CS5 is negated
1.5T-2.44
1.5T-0.8
ns
5
RW negated to address inactive
57.31
–
ns
6
DTACK asserted after CS5 asserted
–
1019T
ns
7
DTACK asserted to RW negated
2T+2.37
3T+6.6
ns
8
Data hold timing after RW negated
1.5T-3.99
–
ns
9
Data ready after CS5 is asserted
–
T
ns
10
EB negated after CS5 is negated
0.5T
0.5T+0.5
ns
11
DTACK pulse width
1T
3T
ns
Note:
1. DTACK asserted means DTACK becomes low level.
2. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
3. CS5 assertion can be controlled by CSA bits. EB assertion can also be programmed by WEA bits in the CS5L register.
4. Address becomes valid and RW asserts at the start of write access cycle.
5. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor
21