MC9328MXS Datasheet, PDF (20/72 Pages) List of Unclassifed Manufacturers – Advance Information

Specifications
3.9.2.2 DTACK Read Cycle DMA Enabled
Address
2
CS5
1
EB
programmable
min 0ns
OE
6
4
9
10
3
RW (logic high)
DTACK
DATABUS
(input to i.MX)
5
7
11
8
Figure 7. DTACK Read Cycle DMA Enabled
Table 14. Read Cycle DMA Enabled: WSC = 111111, DTACK_SEL=0, HCLK=96MHz
Number
Characteristic
3.0 ± 0.3 V
Unit
Minimum
Maximum
1
OE and EB assertion time
See note 3
–
ns
2
CS pulse width
3T
–
ns
3
OE negated before CS5 is negated
0.5T-0.68
0.5T-0.06
ns
4
Address inactive before CS negated
–
0.3
ns
5
DTACK asserted after CS5 asserted
–
1019T
ns
6
DTACK asserted to OE negated
3T+1.83
4T+6.6
ns
7
Data hold timing after OE negated
0
–
ns
8
Data ready after DTACK is asserted
–
T
ns
9
CS deactive to next CS active
T
–
ns
10
OE negate after EB negate
0.06
0.18
ns
11
DTACK pulse width
1T
3T
ns
Note:
1. DTACK asserted means DTACK becomes low level.
2. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
3. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when
EBC bit in CS5L register is clear.
4. Address becomes valid and CS asserts at the start of read access cycle.
5. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
MC9328MXS Advance Information, Rev. 0
20
Freescale Semiconductor