MC9328MXS Datasheet, PDF (50/72 Pages) List of Unclassifed Manufacturers – Advance Information

Specifications
3.9.4 Non-TFT Panel Timing
T1
T1
VSYN
T2
T3
XMAX
T4
T2
HSYN
SCLK
Ts
LD[15:0]
Figure 37. Non-TFT Panel Timing
Table 21. Non TFT Panel Timing Diagram
Symbol
Parameter
Allowed Register Minimum
Value
Actual Value
Unit
T1
HSYN to VSYN delay
T2
HSYN pulse width
T3
VSYN to SCLK
T4
SCLK to HSYN
0
HWAIT2+2
Tpix
0
HWIDTH+1
Tpix
–
0<= T3<=Ts
–
0
HWAIT1+1
Tpix
• VSYN, HSYN and SCLK can be programmed as active high or active low. In the above timing diagram, all
these 3 signals are active high.
• Ts is the shift clock period.
• Ts = Tpix * (panel data bus width).
• Tpix is the pixel clock period which equals LCDC_CLK period * (PCD + 1).
• Maximum frequency of LCDC_CLK is 48 MHz, which is controlled by Peripheral Clock Divider Register.
• Maximum frequency of SCLK is HCLK / 5, otherwise LD output will be wrong.
MC9328MXS Advance Information, Rev. 0
50
Freescale Semiconductor