MC9328MXS Datasheet, PDF (15/72 Pages) List of Unclassifed Manufacturers – Advance Information

5
RESET_IN
HRESET
RESET_OUT
6
Specifications
14 cycles @ CLK32
4
CLK32
HCLK
Figure 4. Timing Relationship with RESET_IN
Table 11. Reset Module Timing Parameter Table
Ref
No.
Parameter
1.8 ± 0.1 V
3.0 ± 0.3 V
Unit
Min
Max
Min Max
1 Width of input POWER_ON_RESET
2 Width of internal POWER_ON_RESET
(CLK32 at 32 kHz)
3 7K to 32K-cycle stretcher for SDRAM reset
4 14K to 32K-cycle stretcher for internal system reset
HRESERT and output reset at pin RESET_OUT
5 Width of external hard-reset RESET_IN
6 4K to 32K-cycle qualifier
note¹
300
7
14
4
4
–
note¹
–
–
300
300 300
ms
7
7
7
Cycles of
CLK32
14
14
14
Cycles of
CLK32
–
4
–
Cycles of
CLK32
4
4
4
Cycles of
CLK32
1. POR width is dependent on the 32 or 32.768 kHz crystal oscillator start-up time. Design margin should allow for
crystal tolerance, i.MX chip variations, temperature impact, and supply voltage influence. Through the process of
supplying crystals for use with CMOS oscillators, crystal manufacturers have developed a working knowledge of
start-up time of their crystals. Typically, start-up times range from 400 ms to 1.2 seconds for this type of crystal.
If an external stable clock source (already running) is used instead of a crystal, the width of POR should be ignored
in calculating timing for the start-up process.
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor
15