MC9328MXS Datasheet, PDF (22/72 Pages) List of Unclassifed Manufacturers – Advance Information

Specifications
3.9.2.4 DTACK Write Cycle DMA Enabled
Address
1
CS5
2
EB
RW
programmable
min 0ns
programmable
min 0ns
3
7
5
10
11
4
OE (logic high)
6
DTACK
9
DATABUS
(output to i.MX)
12
8
Figure 9. DTACK Write Cycle DMA Enabled
Table 16. Write Cycle DMA Enabled: WSC = 111111, DTACK_SEL=0, HCLK=96MHz
Number
Characteristic
3.0 ± 0.3 V
Unit
Minimum
Maximum
1
CS5 assertion time
See note 3
–
ns
2
EB assertion time
See note 3
–
ns
3
CS5 pulse width
3T
–
ns
4
RW negated before CS5 is negated
1.5T-2.44
1.5T-0.8
ns
5
Address inactive after CS negated
–
0.3
ns
6
DTACK asserted after CS5 asserted
–
1019T
ns
7
DTACK asserted to RW negated
2T+2.37
3T+6.6
ns
8
Data hold timing after RW negated
1.5T-3.99
–
ns
9
Data ready after CS5 is asserted
–
T
ns
10
CS deactive to next CS active
T
–
ns
11
EB negate after CS negate
0.5T
0.5T+0.5
ns
12
DTACK pulse width
1T
3T
ns
Note:
1. DTACK asserted means DTACK becomes low level.
2. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
3. CS5 assertion can be controlled by CSA bits. EB assertion also can be programmed by WEA bits in the CS5L register.
4. Address becomes valid and RW asserts at the start of write access cycle.
5.The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
MC9328MXS Advance Information, Rev. 0
22
Freescale Semiconductor