MC9328MXS Datasheet, PDF (23/72 Pages) List of Unclassifed Manufacturers – Advance Information

3.9.2.5 WAIT Read Cycle without DMA
Address
2
CS5
1
programmable
EB
min 0ns
OE
Specifications
3
8
9
5
4
WAIT
DATABUS
10
(input to i.MX)
7
6
11
Figure 10. WAIT Read Cycle without DMA
Table 17. WAIT Read Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
Number
Characteristic
3.0 ± 0.3 V
Unit
Minimum
Maximum
1
OE and EB assertion time
See note 2
–
ns
2
CS5 pulse width
3T
–
ns
3
OE negated to address inactive
56.81
57.28
ns
4
Wait asserted after OE asserted
–
1020T
ns
5
Wait asserted to OE negated
2T+1.57
3T+7.33
ns
6
Data hold timing after OE negated
T-1.49
–
ns
7
Data ready after wait asserted
0
T
ns
8
OE negated to CS negated
1.5T-0.68
1.5T-0.06
ns
9
OE negated after EB negated
0.06
0.18
ns
10
Become low after CS5 asserted
0
1019T
ns
11
Wait pulse width
1T
1020T
ns
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when
EBC bit in CS5L register is clear.
3. Address becomes valid and CS asserts at the start of read access cycle.
4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor
23