MC9328MXS Datasheet, PDF (59/72 Pages) List of Unclassifed Manufacturers – Advance Information

Specifications
Table 27. SDRAM Write Timing Parameter Table (Continued)
Ref
No.
Parameter
1.8 ± 0.1 V
Minimum Maximum
3.0 ± 0.3 V
Unit
Minimum Maximum
8 Data setup time
9 Data hold time
4.0
–
2
–
ns
2.28
–
2
–
ns
1. Precharge cycle timing is included in the write timing diagram.
2. t_RP and t_RCD = SDRAM clock cycle time. These settings can be found in the i.MX reference manual.
SDCLK
CS
13
2
RAS
CAS
6
7
7
WE
ADDR
4
5
BA
ROW/BA
DQ
DQM
Figure 48. SDRAM Refresh Timing Diagram
Table 28. SDRAM Refresh Timing Parameter Table
1.8 ± 0.1 V
3.0 ± 0.3 V
Ref
No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
1
SDRAM clock high-level width
2
SDRAM clock low-level width
2.67
–
4
–
ns
6
–
4
–
ns
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor
59