MC9328MXS Datasheet, PDF (13/72 Pages) List of Unclassifed Manufacturers – Advance Information

Specifications
3.7 DPLL Timing Specifications
Parameters of the DPLL are given in Table 10. In this table, T_ref is a reference clock period after the pre-divider
and T_dck is the output double clock period.
Table 10. DPLL Specifications
Parameter
Test Conditions
Minimum Typical Maximum Unit
Reference clock freq range
Vcc = 1.8V
5
Pre-divider output clock
Vcc = 1.8V
5
freq range
Double clock freq range
Vcc = 1.8V
80
Pre-divider factor (PD)
–
1
Total multiplication factor (MF) Includes both integer and fractional parts
5
MF integer part
–
5
MF numerator
Should be less than the denominator
0
MF denominator
–
1
Pre-multiplier lock-in time
–
–
–
100
MHz
–
30
MHz
–
220
MHz
–
16
–
–
15
–
–
15
–
–
1022
–
–
1023
–
–
312.5
µsec
Freq lock-in time after
full reset
Freq lock-in time after
partial reset
Phase lock-in time after
full reset
Phase lock-in time after
partial reset
Freq jitter (p-p)
Phase jitter (p-p)
Power supply voltage
Power dissipation
FOL mode for non-integer MF
(does not include pre-multi lock-in time)
FOL mode for non-integer MF (does not
include pre-multi lock-in time)
FPL mode and integer MF (does not
include pre-multi lock-in time)
FPL mode and integer MF (does not
include pre-multi lock-in time)
–
Integer MF, FPL mode, Vcc=1.8V
–
FOL mode, integer MF,
f_dck = 100 MHz, Vcc = 1.8V
250
280
300
T_ref
(56 µs)
220
250
270
T_ref
(50 µs)
300
350
400
T_ref
(70 µs)
270
320
370
T_ref
(64 µs)
–
0.005
0.01
2•T_dck
(0.01%)
–
1.0
1.5
ns
(10%)
1.7
–
2.5
V
–
–
4
mW
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor
13