MC9328MXS Datasheet, PDF (54/72 Pages) List of Unclassifed Manufacturers – Advance Information

Specifications
Table 24. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing (Continued)
Symbol
Description
Minimum Corresponding Register Value Unit
T10 VSYN to OE active (Sharp = 0) when VWAIT2 = 0
1
1
Ts
T10 VSYN to OE active (Sharp = 1) when VWAIT2 = 0
2
2
Ts
Note:
•
•
•
•
•
•
Ts is the SCLK period which equals LCDC_CLK / (PCD + 1). Normally LCDC_CLK = 15ns.
VSYN, HSYN and OE can be programmed as active high or active low. In Figure 44, all 3 signals are active low.
The polarity of SCLK and LD[15:0] can also be programmed.
SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period. In Figure 44, SCLK is always
active.
For T9 non-display region, VSYN is non-active. It is used as an reference.
XMAX is defined in pixels.
MC9328MXS Advance Information, Rev. 0
54
Freescale Semiconductor