MC9328MXS Datasheet, PDF (27/72 Pages) List of Unclassifed Manufacturers – Advance Information

3.9.3 EIM External Bus Timing
The following timing diagrams show the timing of accesses to memory or a peripheral.
hclk
hsel_weim_cs[0]
htrans
Seq/Nonseq
hwrite
Read
haddr
V1
hready
weim_hrdata
Last Valid Data
V1
weim_hready
BCLK (burst clock)
ADDR
CS2
R/W
LBA
OE
EBx¹ (EBC²=0)
EBx¹ (EBC²=1)
Last Valid Address
V1
Read
DATA
V1
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 14. WSC = 1, A.HALF/E.HALF
Specifications
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor
27