EN27LN1G08 Datasheet, PDF (8/41 Pages) Eon Silicon Solution Inc. – 1 Gigabit (128 M x 8), 3.3 V NAND Flash Memory

EN27LN1G08
Product Introduction
This device is a 1,056Mbits (1,107,296,256 bits) memory organized as 65,539 rows (pages) by 2,112-
byte columns. Spare 64-byte columns are located from column address of 2,048 to 2,111.
A 2,112-byte data register and 2,112-byte cache register are serially connected to each other. Those
serially connected registers are connected to memory cell arrays for accommodating data transfer
between the I/O buffers and memory cells during page read and page program operations. The memory
array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells
resides in a different page. A block consists of two NAND structured strings. A NAND structure consists
of 32 cells. Total 1,081,344 NAND cells reside in a block. The program and read operations are
executed on a page basis, while the erase operation is executed on a block basis. The memory array
consists of 1,024 separately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is
prohibited on the device.
This device uses addresses multiplexed scheme. This scheme dramatically reduces pin counts and
allows systems upgrades to future densities by maintaining consistency in system board design.
Command, address and data are all written through I/O's by bringing WE# to low while CE# is low.
Those are latched on the rising edge of WE#. Command Latch Enable (CLE) and Address Latch Enable
(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands
require one bus cycle. For example, Reset Command, Status Read Command, etc require just one
cycle bus. Some other commands, like page read and block erase and page program, require two
cycles: one cycle for setup and the other cycle for execution. The total physical space requires 28
addresses, thereby requiring four cycles for addressing: 2 cycle of column address, 2 cycles of row
address, in that order. Page Read and Page Program need the same four address cycles following the
required command input. In Block Erase operation, however, only the 2 cycles of row address are used.
Device operations are selected by writing specific commands into the command register. Below table
defines the specific commands of this device.
The device provides cache program in a block. It is possible to write data into the cache registers while
data stored in data registers are being programmed into memory cells in cache program mode. The
program performance may be dramatically improved by cache program when there are lots of pages of
data to be programmed.
In addition to the enhanced architecture and interface, the device incorporates copy-back program
feature from one page to another page without need for transporting the data to and from the external
buffer memory. Since the time-consuming serial access and data-input cycles are removed, system
performance for solid-state disk application is significantly increased.
Command Set
Function
1st Cycle 2nd Cycle
Acceptable Command during Busy
Read
00h
30h
Read for Copy Back
00h
35h
Read ID
90h
-
Reset
FFh
-
O
Page Program
80h
10h
Cache Program
80h
15h
Copy-Back Program
85h
10h
Block Erase
60h
D0h
Random Data Input(1)
85h
-
Random Data Output(1)
05h
E0h
Read Status
70h
-
O
Note:
1. Random Data Input / Output can be executed in a page.
Caution: Any undefined command inputs are prohibited except for above command set of above table.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. C, Issue Date: 2013/10/03