EN27LN1G08 Datasheet, PDF (27/41 Pages) Eon Silicon Solution Inc. – 1 Gigabit (128 M x 8), 3.3 V NAND Flash Memory

DEVICE OPERATION
EN27LN1G08
Page Read
Page read is initiated by writing 00h-30h to the command register along with four address cycles. After
initial power up, 00h command is latched. Therefore only four address cycles and 30h command
initiates that operation after initial power up. The 2,112 bytes of data within the selected page are
transferred to the data registers in less than t_R. The system controller can detect the completion of this
data transfer (t_R) by analyzing the output of R/B# pin. Once the data in a page is loaded into the data
registers, they may be read out in 25ns cycle time by sequentially pulsing RE#. The repetitive high to
low transitions of the RE# clock make the device output the data starting from the selected column
address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing
random data output command. The column address of next data, which is going to be out, may be
changed to the address which follows random data output command.
Random data output can be operated multiple times regardless of how many times it is done in a page.
Read Operation
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. C, Issue Date: 2013/10/03