EN27LN1G08 Datasheet, PDF(32/41 Page) Eon Silicon Solution Inc. – 1 Gigabit (128 M x 8), 3.3 V NAND Flash Memory

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EN27LN1G08 Datasheet, PDF (32/41 Pages) Eon Silicon Solution Inc. – 1 Gigabit (128 M x 8), 3.3 V NAND Flash Memory

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Page Copy-Back Program Operation with Random Data Input

EN27LN1G08

Block Erase

The Erase operation is done on a block basis. Block address loading is accomplished in two cycles

initiated by an Erase Setup command (60h). Only address A18 to A27 is valid while A12 to A17 is

ignored. The Erase Confirm command (D0h) following the block address loading initiates the internal

erasing process. This two-step sequence of setup followed by execution command ensures that

memory contents are not accidentally erased due to external noise conditions.

At the rising edge of WE# after the erase confirm command input, the internal write controller handles

erase and erase-verify. When the erase operation is completed, the Write Status Bit (I/O0) may be

checked.

Block Erase Operation

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

Rev. C, Issue Date: 2013/10/03

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