EN27LN1G08 Datasheet, PDF (29/41 Pages) Eon Silicon Solution Inc. – 1 Gigabit (128 M x 8), 3.3 V NAND Flash Memory

EN27LN1G08
Page Program
The device is programmed basically on a page basis, but it does allow multiple partial page
programming of a word or consecutive bytes up to 2,112, in a single page program cycle. The number
of consecutive partial page programming operation within the same page without an intervening erase
operation must not exceed 4 times for a single page. The addressing should be done in sequential order
in a block. A page program cycle consists of a serial data loading period in which up to 2,112 bytes of
data may be loaded into the data register, followed by a non-volatile programming period where the
loaded data is programmed into the appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the
four cycle address inputs and then serial data loading. The words other than those to be programmed
do not need to be loaded. The device supports random data input in a page. The column address for the
next data, which will be entered, may be changed to the address which follows random data input
command (85h). Random data input may be operated multiple times regardless of how many times it is
done in a page.
The Page Program confirm command (10h) initiates the programming process. Writing 10h alone
without previously entering the serial data will not initiate the programming process. The internal write
state controller automatically executes the algorithms and timings necessary for program and verify,
thereby freeing the system controller for other tasks. Once the program process starts, the Read Status
Register command may be entered, with RE# and CE# low, to read the status register. The system
controller can detect the completion of a program cycle by monitoring the R/B# output, or the Status bit
(I/O6) of the Status Register. Only the Read Status command and Reset command are valid while
programming is in progress. When the Page Program is complete, the Write Status Bit
(I/O0) may be checked. The internal write verify detects only errors for "1"s that are not successfully
programmed to "0"s. The command register remains in Read Status command mode until another valid
command is written to the command register.
Program & Read Status Operation
Random Data Input In a page
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. C, Issue Date: 2013/10/03