EN27LN1G08 Datasheet, PDF (35/41 Pages) Eon Silicon Solution Inc. – 1 Gigabit (128 M x 8), 3.3 V NAND Flash Memory

ID Definition Table
ID Access command = 90h
Maker Code Device Code
92h
F1h
3^rd Cycle
80h
4^th Cycle
95h
EN27LN1G08
5^th Cycle
40h
1^st Byte
2^nd Byte
3^rd Byte
4^th Byte
5^th Byte
Description
Maker Code
Device Code
Internal Chip Number, Cell Type, Number of Simultaneously
Programmed Pages, Etc.
Page Size, Block Size, Redundant Area Size, Organization,
Serial Access Minimum
Plane Number, Plane Size
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is
in busy state during random read, program or erase mode, the reset operation will abort these
operations. The contents of memory cells being altered are no longer valid, as the data will be partially
programmed or erased. The command register is cleared to wait for the next command, and the Status
Register is cleared to value C0h when WP# is high. If the device is already in reset state a new reset
command will be accepted by the command register. The R/B# pin changes to low for t_RST after the
Reset command is written. Refer to Figure below.
Device Status
Operation mode
After Power-up
00h Command is latched
After Reset
Waiting for next command
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. C, Issue Date: 2013/10/03