EN27LN1G08 Datasheet, PDF (10/41 Pages) Eon Silicon Solution Inc. – 1 Gigabit (128 M x 8), 3.3 V NAND Flash Memory

EN27LN1G08
VALID BLOCK
Symbol
Min.
Typ.
Max.
Unit
N_VB
1,004
-
1,024
Blocks
Note:
1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may
develop while being used. The number of valid blocks is presented as first shipped. Invalid blocks
are defined as blocks that contain one or more bad bits which cause status failure during program
and erase operation. Do not erase or program factory-marked bad blocks. Refer to the attached
technical notes for appropriate management of initial invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K
program/erase cycles with 1 bit/528 bytes ECC.
AC TEST CONDITION
(T_A = 0 to 70°C or – 40°C to 85°C, V_CC=2.7V~3.6V, unless otherwise noted)
Parameter
Condition
Input Pulse Levels
Input Rise and Fall Times
0V to V_CC
5 ns
Input and Output Timing Levels
Output Load
V_CC /2
1 TTL Gate and C_L=50pF
CAPACITANCE
(T_A = 25°C, V_CC=3.3V, f =1.0MHz)
Item
Symbol
Test Condition
Input / Output Capacitance
C_I/O
V_IL = 0V
Input Capacitance
C_IN
V_IN = 0V
Note: Capacitance is periodically sampled and not 100% tested.
Min.
-
-
Max.
Unit
8
pF
8
pF
MODE SELECTION
CLE
ALE
CE#
WE#
RE#
WP#
Mode
H
L
L
Rising
H
X
Read Mode ^{Command Input}
L
H
L
Rising
H
X
Address Input (4 clock)
H
L
L
Rising
H
H
Command Input
Write Mode
L
H
L
Rising
H
H
Address Input (4 clock)
L
L
L
Rising
H
H
Data Input
L
L
L
H
Falling
X
Data Output
X
X
X
X
H
X
During Read (Busy)
X
X
X
X
X
H
During Program (Busy)
X
X
X
X
X
H
During Erase (Busy)
X
X⁽¹⁾
X
X
X
L
Write Protect
X
X
H
X
X
0V/V_CC(2) Stand-by
Note:
1. X can be V_IL or V_IH.
2. WP# should be biased to CMOS high or CMOS low for stand-by.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. C, Issue Date: 2013/10/03