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BCM4339 Preliminary Data Sheet
PCI Express Interface (FCBGA Package Only)
PCI Express Interface (FCBGA Package Only)
The PCI Express (PCIe^™) core on the BCM4339 is a high-performance serial I/O interconnect that is protocol
compliant and electrically compatible with the PCI Express Base Specification (revision 3.0 compliant Gen1
interface). This core contains all the necessary blocks, including logical and electrical functional subblocks to
perform PCIe functionality and maintain high-speed links, using existing PCI system configuration software
implementations without modification.
Organization of the PCIe core is in logical layers: Transaction Layer, Data Link Layer, and Physical Layer, as
shown in Figure 34. A configuration or link management block is provided for enumerating the PCIe
configuration space and supporting generation and reception of System Management Messages by
communicating with PCIe layers.
Each layer is partitioned into dedicated transmit and receive units that allow point-to-point communication
between the host and BCM4339 device. The transmit side processes outbound packets while the receive side
processes inbound packets. Packets are formed and generated in the Transaction and Data Link Layer for
transmission onto the high-speed links and onto the receiving device. A header is added at the beginning to
indicate the packet type and any other optional fields.
Figure 34: PCI Express Layer Model
HW/SW Interface
HW/SW Interface
Transaction
Layer
Transaction
Layer
Data Link
Layer
Physical Layer
Logical Subblock
Electrical Subblock
TX
RX
Data Link
Layer
Physical Layer
Logical Subblock
Electrical Subblock
TX
RX
Broadcom^®
November 17, 2014 • 4339-DS106-R
Page 83