BCM4339XKWBGT Datasheet, PDF (82/183 Pages) Cypress Semiconductor – Single-Chip 5G WiFi IEEE 802.11ac MAC/Baseband/Radio with Integrated Bluetooth 4.1 and FM Receiver

BCM4339 Preliminary Data Sheet
Generic SPI Mode
Table 18: gSPI Registers (Cont.)
Address
x0002
x0003
x0004
x0005
x0006–
x0007
x0008–
x000B
x000C–
x000D
x000E–
x000F
x0010–
x0011
x0014–
x0017
x0018–
x001B
Register
Status enable
Interrupt with status
Response delay for
all
Reserved
Interrupt register
Interrupt register
Interrupt enable
register
Status register
F1 info register
F2 info register
F3 info register
Test–Read only
register
Test–R/W register
Bit Access Default Description
0 R/W 1
0: no status sent to host after read/write
1: status sent to host after read/write
1 R/W 0
0: do not interrupt if status is sent
1: interrupt host even if status is sent
2 R/W 0
0: response delay applicable to F1 read only
1: response delay applicable to all function read
––
–
–
0 R/W 0
Requested data not available; Cleared by writing a
1 to this location
1R
0
F2/F3 FIFO underflow due to last read
2R
0
F2/F3 FIFO overflow due to last write
5R
0
F2 packet available
6R
0
F3 packet available
7R
0
F1 overflow due to last write
5R
0
F1 Interrupt
6R
0
F2 Interrupt
7R
0
F3 Interrupt
15:0 R/W/U 16'hE0E7 Particular Interrupt is enabled if a corresponding bit
is set
31:0 R
32'h0000 Same as status bit definitions
0R
1R
13:2 R/U
0 R/U
1R
15:2 R/U
0 R/U
1R
15:2 R/U
31:0 R
31:0 R/W/U
1
0
12'h40
1
0
14'h800
1
0
14'h800
32'hFEE
DBEAD
32'h0000
0000
F1 enabled
F1 ready for data transfer
F1 max packet size
F2 enabled
F2 ready for data transfer
F2 max packet size
F3 enabled
F3 ready for data transfer
F3 max packet size
This register contains a predefined pattern, which
the host can read and determine if the gSPI
interface is working properly.
This is a dummy register where the host can write
some pattern and read it back to determine if the
gSPI interface is working properly.
Broadcom^®
November 17, 2014 • 4339-DS106-R
Page 81