BCM4339XKWBGT Datasheet, PDF (83/183 Pages) Cypress Semiconductor – Single-Chip 5G WiFi IEEE 802.11ac MAC/Baseband/Radio with Integrated Bluetooth 4.1 and FM Receiver

BCM4339 Preliminary Data Sheet
Figure 33 shows the WLAN boot-up sequence from power-up to firmware download.
Figure 33: WLAN Boot-Up Sequence
Generic SPI Mode
VBAT*
VDDIO
WL_REG_ON
VDDC
(from internal PMU)
Internal POR
< 950 µs
< 104 ms
< 4 ms
After a fixed delay following Internal POR and WL_REG_ON going high,
the device responds to host F0 (address 0x14) reads.
Device requests for reference clock
Host Interaction:
Host polls F0 (address 0x14) until it reads a
predefined pattern.
8 ms
After 8 ms the reference clock is
assumed to be up. Access to PLL
registers is possible.
Host sets wake-up-wlan bit and
waits 8 ms, the maximum time for
reference clock availability.
After 8 ms, host programs PLL
registers to set crystal frequency
Chip active interrupt is asserted after the PLL locks
Host downloads
code.
*Notes:
1. VBAT should not rise 10%–90% faster than 40 microseconds.
2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high.
Broadcom^®
November 17, 2014 • 4339-DS106-R
Page 82