BCM4339XKWBGT Datasheet, PDF (106/183 Pages) Cypress Semiconductor – Single-Chip 5G WiFi IEEE 802.11ac MAC/Baseband/Radio with Integrated Bluetooth 4.1 and FM Receiver

BCM4339 Preliminary Data Sheet
Signal Descriptions
Signal Descriptions
The signal name, type, and description of each pin in the BCM4339 is listed in Table 20. The symbols shown
under Type indicate pin directions (I/O = bidirectional, I = input, O = output) and the internal pull-up/pull-down
characteristics (PU = weak internal pull-up resistor and PD = weak internal pull-down resistor), if any.
Table 20: FCFBGA, WLBGA, and WLCSP Signal Descriptions
WLBGA FCFBGA WLCSP
Ball#
Ball#
Bump#
Signal Name
WLAN and Bluetooth RF Signal Interface
N7
W10
118
WRF_RFIN_2G
N5
W8
93
N12
W18
102
N8
W12
115
N11
W16
106
J7
V11
121
BT_RF_TX
WRF_RFIN_5G
WRF_RFOUT_2G
WRF_RFOUT_5G
WRF_TSSI_A
H7
V10
122
RF Switch Control Lines
F12
J19
145
F11
J17
146
E12
J18
147
E11
G19
148
D12
H17
149
F8
G17
150
H9
G18
151
G7
J16
152
E10
G16
153
F5
H16
154
WLAN PCI Express Interface
–
A19
–
WRF_RES_EXT/
WRF_GPIO_OUT/
WRF_TSSI_G
RF_SW_CTRL_0
RF_SW_CTRL_1
RF_SW_CTRL_2
RF_SW_CTRL_3
RF_SW_CTRL_4
RF_SW_CTRL_5
RF_SW_CTRL_6
RF_SW_CTRL_7
RF_SW_CTRL_8
RF_SW_CTRL_9
PCIE_CLKREQ_L
–
B16
–
PERST_L
Type Description
I 2.4 GHz Bluetooth and WLAN
receiver shared input.
O Bluetooth PA output.
I 5 GHz WLAN receiver input.
O 2.4 GHz WLAN PA output.
O 5 GHz WLAN PA output.
I 5 GHz TSSI input from an
optional external power
amplifier/power detector.
I/O GPIO or 2.4 GHz TSSI input
from an optional external power
amplifier/power detector.
O Programmable RF switch
O
control lines. The control lines
are programmable via the
O _{driver and NVRAM file.}
O
O
O
O
O
O
O
OD PCIe clock request signal which
indicates when the REFCLK to
the PCIe interface can be
gated.
1 = the clock can be gated
0 = the clock is required
I (PU) PCIe System Reset. This input
is the PCIe reset as defined in
the PCIe base specification
version 1.1.
Broadcom^®
November 17, 2014 • 4339-DS106-R
Page 105