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BCM4339XKWBGT Datasheet, PDF (169/183 Pages) Cypress Semiconductor – Single-Chip 5G WiFi IEEE 802.11ac MAC/Baseband/Radio with Integrated Bluetooth 4.1 and FM Receiver | |||
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BCM4339 Preliminary Data Sheet
gSPI Signal Timing
The gSPI host and device always use the rising edge of clock to sample data.
Figure 52: gSPI Timing
SDIO/gSPI Timing
Table 60: gSPI Timing Parameters
Parameter
Symbol Minimum
Maximum
Units Note
Clock period
Clock high/low
T1
T2/T3
20.8
â
ns
(0.45 Ã T1) â T4 (0.55 Ã T1) â T4 ns
Fmax = 48 MHz
â
Clock rise/fall timea T4/T5
â
2.5
ns Measured from 10% to 90% of
VDDIO
Input setup time T6
5.0
â
ns Setup time, SIMO valid to
SPI_CLK active edge
Input hold time
T7
5.0
â
ns Hold time, SPI_CLK active edge
to SIMO invalid
Output setup time T8
5.0
â
ns Setup time, SOMI valid before
SPI_CLK rising
Output hold time T9
5.0
â
CSX to clockb
â
7.86
â
Clock to CSXa
â
â
â
ns Hold time, SPI_CLK active edge
to SOMI invalid
ns CSX fall to 1st rising edge
ns Last falling edge to CSX high
a. Limit applies when SPI_CLK = Fmax. For slower clock speeds, longer rise/fall times are acceptable provided that
the transitions are monotonic and the setup and hold time limits are complied with.
b. SPI_CSx remains active for entire duration of gSPI read/write/write-read transaction (overall words for multiple-
word transaction).
Broadcom®
November 17, 2014 ⢠4339-DS106-R
Page 168
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