BCM4339XKWBGT Datasheet, PDF (81/183 Pages) Cypress Semiconductor – Single-Chip 5G WiFi IEEE 802.11ac MAC/Baseband/Radio with Integrated Bluetooth 4.1 and FM Receiver

BCM4339 Preliminary Data Sheet
Generic SPI Mode
gSPI Host-Device Handshake
To initiate communication through the gSPI after power-up, the host needs to bring up the WLAN/Chip by writing
to the wake-up WLAN register bit. Writing a 1 to this bit will start up the necessary crystals and PLLs so that the
BCM4339 is ready for data transfer. The device can signal an interrupt to the host indicating that the device is
awake and ready. This procedure also needs to be followed for waking up the device in sleep mode. The device
can interrupt the host using the WLAN IRQ line whenever it has any information to pass to the host. On getting
an interrupt, the host needs to read the interrupt and/or status register to determine the cause of interrupt and
then take necessary actions.
Boot-Up Sequence
After power-up, the gSPI host needs to wait 150 ms for the device to be out of reset. For this, the host needs to
poll with a read command to F0 addr 0x14. Address 0x14 contains a predefined bit pattern. As soon as the host
gets a response back with the correct register content, it implies that the device has powered up and is out of
reset. After that, the host needs to set the wakeup-WLAN bit (F0 reg 0x00 bit 7). The wakeup-WLAN issues a
clock request to the PMU.
For the first time after power-up, the host must wait for the availability of low power clock inside the device. Once
that is available, the host must write to a PMU register to set the crystal frequency, which turns on the PLL. After
the PLL is locked, the chipActive interrupt is issued to the host. This interrupt indicates the device awake/ready
status. See Table 18 for information on gSPI registers.
In Table 18, the following notation is used for register access:
• R: Readable from host and CPU
• W: Writable from host
• U: Writable from CPU
Address Register
x0000 Word length
Endianness
High-speed mode
Interrupt polarity
Wake-up
x0001 Response delay
Table 18: gSPI Registers
Bit Access Default
0 R/W/U 0
1 R/W/U 0
4 R/W/U 1
5 R/W/U 1
7 R/W 0
7:0 R/W/U 8‘h04
Description
0: 16 bit word length
1: 32 bit word length
0: Little Endian
1: Big Endian
0: Normal mode. RX and TX at different edges.
1: High speed mode. RX and TX on same edge
(default).
0: Interrupt active polarity is low
1: Interrupt active polarity is high (default)
A write of 1 will denote a wake-up command from
the host to the device. This will be followed by an F2
Interrupt from the gSPI device to the host, indicating
device awake status.
Configurable read response delay in multiples of 8
bits
Broadcom^®
November 17, 2014 • 4339-DS106-R
Page 80