BCM4339XKWBGT Datasheet, PDF (74/183 Pages) Cypress Semiconductor – Single-Chip 5G WiFi IEEE 802.11ac MAC/Baseband/Radio with Integrated Bluetooth 4.1 and FM Receiver

BCM4339 Preliminary Data Sheet
WLAN Host Interfaces
Section 10: WLAN Host Interfaces
SDIO v3.0
The BCM4339 WLAN section supports SDIO version 3.0, including the new UHS-I modes:
• DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3V signaling).
• HS: High speed up to 50 MHz (3.3V signaling).
• SDR12: SDR up to 25 MHz (1.8V signaling).
• SDR25: SDR up to 50 MHz (1.8V signaling).
• SDR50: SDR up to 100 MHz (1.8V signaling).
• SDR104: SDR up to 208 MHz (1.8V signaling).
• DDR50: DDR up to 50 MHz (1.8V signaling).
Note: The BCM4339 is backward compatible with SDIO v2.0 host interfaces.
The SDIO interface also has the ability to map the interrupt signal on to a GPIO pin for applications requiring an
interrupt different from the one provided by the SDIO interface. The ability to force control of the gated clocks
from within the device is also provided. SDIO mode is enabled by strapping options. Refer to Table 21 on
page 114 WLAN GPIO Functions and Strapping Options.
The following three functions are supported:
• Function 0 Standard SDIO function (Max. BlockSize/ByteCount = 32B)
• Function 1 Backplane Function to access the internal system-on-chip (SoC) address space
(Max. BlockSize/ByteCount = 64B)
• Function 2 WLAN Function for efficient WLAN packet transfer through DMA
(Max. BlockSize/ByteCount = 512B)
SDIO Pins
Table 16: SDIO Pin Description
DATA0
DATA1
DATA2
DATA3
CLK
CMD
SD 4-Bit Mode
Data line 0
DATA
Data line 1 or Interrupt IRQ
Data line 2 or Read Wait RW
Data line 3
N/C
Clock
CLK
Command line
CMD
SD 1-Bit Mode
Data line
Interrupt
Read Wait
Not used
Clock
Command line
DO
IRQ
NC
CS
SCLK
DI
gSPI Mode
Data output
Interrupt
Not used
Card select
Clock
Data input
Broadcom^®
November 17, 2014 • 4339-DS106-R
Page 73