BCM4339XKWBGT Datasheet, PDF (115/183 Pages) Cypress Semiconductor – Single-Chip 5G WiFi IEEE 802.11ac MAC/Baseband/Radio with Integrated Bluetooth 4.1 and FM Receiver

BCM4339 Preliminary Data Sheet
WLAN GPIO Signals and Strapping Options
WLAN GPIO Signals and Strapping Options
The pins listed in Table 21 are sampled at power-on reset (POR) to determine the various operating modes.
Sampling occurs a few milliseconds after an internal POR or deassertion of the external POR. After the POR,
each pin assumes the GPIO or alternative function specified in the signal descriptions table. Each strapping
option pin has an internal pull-up (PU) or pull-down (PD) resistor that determines the default mode. To change
the mode, connect an external PU resistor to VDDIO or a PD resistor to GND, using a 10 kΩ resistor or less.
Note: Refer to the reference board schematics for more information.
Table 21: WLAN GPIO Functions and Strapping Options
Pin Name
GPIO_7
GPIO_8
GPIO_14
SDIO_CLK
SDIO_DATA_2
FCBGA
Pin #
B7
E8
A3
B11
C9
WLBGA
Pin #
D4
H1
–
B11
D10
a. See Table 22, Table 23, and Table 24.
WLCSP
Pin #
196
197
202
171
175
Default
Function
1
0
0
1
1
Description
SDIO_SEL^a
SDIO_PADVDDIO
PCIE_DISABLE
CPU-LESS/SPROM_DISABLE^a
SPI_SEL^a
SDIO_SEL
1
1
0
0
0
Table 22: SDIO/gSPI I/O Voltage Selection (All Packages)
SPI_SEL
X
X
1
1
0
SDIO_PADVDDIO
0
1
0
1
X
Mode
1.8V I/O
3.3V I/O
1.8V I/O
3.3V I/O
3.3V I/O
Broadcom^®
November 17, 2014 • 4339-DS106-R
Page 114