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BCM4339 Preliminary Data Sheet
UART Interface
UART Interface
One 2-wire UART interface can be enabled by software as an alternate function on GPIO pins (see
Table 28: “BCM4339 GPIO/SDIO Alternative Signal Functions,” on page 118). Provided primarily for debugging
during development, this UART enables the BCM4339 to operate as RS-232 data termination equipment (DTE)
for exchanging and managing data with other serial devices. It is compatible with the industry standard 16550
UART, and provides a FIFO size of 64 × 8 in each direction.
JTAG Interface
The BCM4339 supports the IEEE 1149.1 JTAG boundary scan standard for performing device package and
PCB assembly testing during manufacturing. In addition, the JTAG interface allows Broadcom to assist
customers by using proprietary debug and characterization test tools during board bringup. Therefore, it is highly
recommended to provide access to the JTAG pins by means of test points or a header on all PCB designs.
See Table 28: “BCM4339 GPIO/SDIO Alternative Signal Functions,” on page 118 for JTAG pin assignments.
SPROM Interface (FCBGA Package only)
For use only with the PCIe Interface in the FCBGA package, various hardware configuration parameters may
be stored in an external SPROM instead of the OTP. The SPROM is read by system software after device reset.
In addition, depending on the board design, customer-specific parameters may be stored in SPROM.
The four SPROM control signals —SPROM_CS, SPROM_CLK, SPROM_DIN, and SPROM_DOUT are
multiplexed on the SDIO interface (see Table 28: “BCM4339 GPIO/SDIO Alternative Signal Functions,” on
page 118 for additional details). By default, the SPROM interface supports 2 kbit serial SPROMs, and it can also
support 4 kbit and 16 kbit serial SPROMs by using the appropriate strapping option.
Broadcom^®
November 17, 2014 • 4339-DS106-R
Page 72