CS42L52 Datasheet, PDF (70/82 Pages) Cirrus Logic – Low Power, Stereo CODEC w/Headphone & Speaker Amps

CS42L52
6.35.3 Noise Gate Threshold and Boost
THRESH sets the threshold level of the noise gate. Input signals below the threshold level will be attenu-
ated to -96 dB. NG_BOOST configures a +30 dB boost to the threshold settings.
THRESH[2:0]
000
001
010
011
100
101
110
111
Application:
Minimum Setting (NG_BOOST = ‘0’b)
-64 dB
-67 dB
-70 dB
-73 dB
-76 dB
-82 dB
Reserved
Reserved
“Noise Gate” on page 28
Minimum Setting (NG_BOOST = ‘1’b)
-34 dB
-37 dB
-40 dB
-43 dB
-46 dB
-52 dB
-58 dB
-64 dB
6.35.4 Noise Gate Delay Timing
Sets the delay time before the noise gate attacks.
NGDELAY[1:0]
00
01
10
11
Application:
Delay Setting
50 ms
100 ms
150 ms
200 ms
“Noise Gate” on page 28
Note: The Noise Gate attack rate is a function of the sampling frequency, Fs, and the ANLGSFTx (“Ch.
x Analog Soft Ramp” on page 49) and ANLGZCx (“Ch. x Analog Zero Cross” on page 49) setting unless
the respective disable bit (“ALCx Soft Ramp Disable” on page 55 or “ALCx Zero Cross Disable” on
page 55) is enabled.
6.36 Status (Address 2Eh) (Read Only)
For all bits in this register, a “1” means the associated error condition has occurred at least once since the
register was last read. A”0” means the associated error condition has NOT occurred since the last reading
of the register. Reading the register resets all bits to 0.
7
Reserved
6
5
4
3
2
1
0
SPCLKERR DSPAOVFL DSPBOVFL PCMAOVFL PCMBOVFL ADCAOVFL ADCBOVFL
6.36.1 Serial Port Clock Error (Read Only)
Indicates the status of the MCLK to LRCK ratio.
SPCLKERR
0
1
Application:
Serial Port Clock Status:
MCLK/LRCK ratio is valid.
MCLK/LRCK ratio is not valid.
“Serial Port Clocking” on page 34
Note: On initial power up and application of clocks, this bit will report ‘1’b as the serial port re-synchro-
nizes.
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DS680A1