CS42L52 Datasheet, PDF (24/82 Pages) Cirrus Logic – Low Power, Stereo CODEC w/Headphone & Speaker Amps

POWER CONSUMPTION See (Note 20).
Operation
Power Ctl. Registers
02h
03h
04h
CS42L52
Typical Current (mA)
i_VHP i_VA
i_VD
i_VL
i_VP
Total
VL=3.3V VP=3.7V _Power
(Note 23)
(mW_rms)
V
1 _{Off (Note 21)}
x x x x x x x x x x x x 1.8 0.00
2.5 0.00
2 Standby (Note 22)
x x x x 1 x x x x x x x 1.8 0.00
2.5 0.00
3 Mono Record
ADC 1 1 1 0 0 1 1 1 11 11 11 11 1.8 0.00
2.5 0.00
PGA to ADC 1 0 1 0 0 1 1 1 11 11 11 11 1.8 0.00
2.5 0.00
MIC to PGA to ADC 1 0 1 0 0 1 0 0 11 11 11 11 1.8 0.00
(with Bias)
2.5 0.00
MIC to PGA to ADC 1 0 1 0 0 1 0 1 11 11 11 11 1.8 0.00
(no Bias)
2.5 0.00
4 Stereo Record
ADC 1 1 0 0 0 1 1 1 11 11 11 11 1.8 0.00
2.5 0.00
PGA to ADC 0 0 0 0 0 1 1 1 11 11 11 11 1.8 0.00
2.5 0.00
MIC to PGA to ADC 0 0 0 0 0 0 0 1 11 11 11 11 1.8 0.00
(no Bias)
2.5 0.00
5 Mono Playback to Headphone 1 1 1 1 0 1 1 1 10 11 11 11 1.8 1.59
2.5 2.07
6 Mono Playback to Speaker
1 1 1 1 0 1 1 1 11 11 10 10 1.8 0.00
2.5 0.00
7 Stereo Playback to Headphone 1 1 1 1 0 1 1 1 10 10 11 11 1.8 2.77
2.5 3.27
8 Stereo Playback to Speaker
1 1 1 1 0 1 1 1 11 11 10 10 1.8 0.00
2.5 0.00
9 Stereo Passthru to Headphone 1 1 1 1 0 1 1 1 10 10 11 11 1.8 2.79
2.5 3.18
10 Mono Record & Playback
1 0 1 0 0 1 1 1 11 10 11 11 1.8 1.77
PGA in (no MIC) to Mono HP
2.5 2.13
11 Phone Monitor
1 0 1 0 0 1 0 0 11 10 11 11 1.8 1.76
MIC (w/bias) in to Mono Out
2.5 2.15
12 Stereo Record & Playback
0 0 0 0 0 1 1 1 10 10 11 11 1.8 2.76
PGA in (no MIC) to St. HP Out
2.5 3.21
13 Stereo Rec. & Full Playback
0 0 0 0 0 1 1 1 10 10 10 10 1.8 3.49
PGA (no MIC) to St. HP & SPK
2.5 3.95
0.00
0.00
0.00
0.00
1.67
1.87
2.1
2.3
3.48
3.71
3.15
3.37
2.31
2.53
3.18
3.42
5.32
5.57
1.99
2.62
0.20
0.22
2.00
2.63
0.20
0.22
1.91
2.14
3.95
4.77
5.33
6.19
5.05
5.90
5.24
6.10
0.00
0.00
0.01
0.02
2.32
3.72
2.31
3.72
2.32
3.72
2.32
3.73
2.37
3.82
2.37
3.81
2.37
3.81
2.72
4.27
4.42
6.77
2.91
4.28
4.38
6.80
1.06
1.81
4.28
6.63
4.28
6.69
4.64
7.17
7.20
10.46
0.00
0.00
0.03
0.03
0.03
0.03
0.03
0.03
0.03
0.01
0.01
0.01
0.01
0.01
0.03
0.03
0.03
0.03
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
3.30
0.00
3.30
0.00
0.00
0.00
0.00
3.30
0.00
0.00
0.02
0.05
7.24
14.05
7.99
15.13
10.49
18.65
9.90
17.83
8.48
15.95
10.04
18.15
13.90
23.53
11.36
22.43
20.54
29.71
13.84
25.48
20.47
29.79
10.39
17.85
18.05
33.90
20.52
37.65
22.46
40.78
40.94
63.56
20. Unless otherwise noted, test conditions are as follows: All zeros input, slave mode, sample rate =
48 kHz; No load. Digital (VD) and logic (VL) supply current will vary depending on speed mode and mas-
ter/slave operation.
21. RESET pin 25 held LO, all clocks and data lines are held LO.
22. RESET pin 25 held HI, all clocks and data lines are held HI.
23. VL current will slightly increase in master mode.
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DS680A1