CS42L52 Datasheet, PDF (38/82 Pages) Cirrus Logic – Low Power, Stereo CODEC w/Headphone & Speaker Amps

CS42L52
4.11 Control Port Operation
The control port is used to access the registers allowing the CODEC to be configured for the desired oper-
ational modes and formats. The operation of the control port may be completely asynchronous with respect
to the audio sample rates. However, to avoid potential interference problems, the control port pins should
remain static if no operation is required.
The control port operates using an I²C interface with the CODEC acting as a slave device.
4.11.1 I²C Control
SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. The signal tim-
ings for a read and write cycle are shown in Figure 20 and Figure 21. A Start condition is defined as a
falling transition of SDA while the clock is high. A Stop condition is defined as a rising transition of SDA
while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the
CS42L52 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low
for a write).
The upper 7 bits of the address field are fixed at 1001010. To communicate with the CS42L52, the chip
address field, which is the first byte sent to the CS42L52, should match 1001010. The eighth bit of the
address is the R/W bit. If the operation is a write, the next byte is the Memory Address Pointer (MAP),
which selects the register to be read or written. If the operation is a read, the contents of the register point-
ed to by the MAP will be output. Setting the auto-increment bit in MAP allows successive reads or writes
of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the
CS42L52 after each input byte is read and is input to the CS42L52 from the microcontroller after each
transmitted byte.
SCL
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 24 25 26 27 28
CHIP ADDRESS (WRITE)
MAP BYTE
DATA
DATA +1
SDA
1 0010 10 0
START
INCR 6 5 4 3 2 1 0
76
ACK
ACK
10
76
ACK
10
Figure 20. Control Port Timing, I²C Write
DATA +n
76 10
ACK
STOP
SCL
SDA
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
CHIP ADDRESS (WRITE)
MAP BYTE
STOP
CHIP ADDRESS (READ)
DATA
DATA +1 DATA + n
1 0 0 1 0100
INCR 6 5 4 3 2 1 0
1 0 0 1 0 101
70
70
70
START
ACK
ACK
START
ACK
ACK
NO
ACK _STOP
Figure 21. Control Port Timing, I²C Read
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in Figure 21, the write operation is aborted after the acknowledge for the MAP byte by sending a stop con-
dition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition.
Send 10010100 (chip address & write operation).
Receive acknowledge bit.
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DS680A1