CS42L52 Datasheet, PDF (22/82 Pages) Cirrus Logic – Low Power, Stereo CODEC w/Headphone & Speaker Amps

SWITCHING SPECIFICATIONS - I²C CONTROL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL, SDA C_L = 30 pF)
Parameters
Symbol
Min
SCL Clock Frequency
f_scl
-
RESET Rising Edge to Start
t_irs
500
Bus Free Time Between Transmissions
t_buf
4.7
Start Condition Hold Time (prior to first clock pulse)
t_hdst
4.0
Clock Low time
t_low
4.7
Clock High Time
t_high
4.0
Setup Time for Repeated Start Condition
t_sust
4.7
SDA Hold Time from SCL Falling
(Note 16)
t_hdd
0
SDA Setup time to SCL Rising
t_sud
250
Rise Time of SCL and SDA
t_rc
-
Fall Time SCL and SDA
t_fc
-
Setup Time for Stop Condition
t_susp
4.7
Acknowledge Delay from SCL Falling
t_ack
300
16. Data must be held for sufficient time to bridge the transition time, t_fc, of SCL.
Max
100
-
-
-
-
-
-
-
-
1
300
-
1000
CS42L52
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
RST
t _irs
Stop
Start
Repeated
Start
SDA
t _buf
t _hdst
t _high
t _hdst
tf
SCL
t _low t _hdd
t _sud
t _sust
tr
Figure 4. Control Port Timing - I²C
Stop
t _susp
22
DS680A1