CS42L52 Datasheet, PDF (21/82 Pages) Cirrus Logic – Low Power, Stereo CODEC w/Headphone & Speaker Amps

CS42L52
SWITCHING SPECIFICATIONS - SERIAL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL, SDOUT C_LOAD = 15 pF.)
Parameters
Symbol Min
Max Units
RESET pin Low Pulse Width
(Note 14)
1
-
ms
MCLK Frequency (Note 15)
(See “Serial Port Clock- MHz
ing” on page 34)
MCLK Duty Cycle
Slave Mode
45
55
%
Input Sample Rate (LRCK)
F_s
(See “Serial Port Clock- kHz
ing” on page 34)
LRCK Duty Cycle
SCLK Frequency
SCLK Duty Cycle
45
55
%
1/t_P
-
64•F_s
Hz
45
55
%
LRCK Setup Time Before SCLK Rising Edge
LRCK Edge to SDOUT MSB Output Delay
SDOUT Setup Time Before SCLK Rising Edge
SDOUT Hold Time After SCLK Rising Edge
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
Master Mode
t_s(LK-SK)
40
t_d(MSB)
-
t_s(SDO-SK)
20
t_h(SK-SDO)
30
t_s(SD-SK)
20
t_h
20
-
ns
52
ns
-
ns
-
ns
-
ns
-
ns
Output Sample Rate (LRCK)
LRCK Duty Cycle
All Speed Modes F_s
(See “Serial Port Clock- Hz
ing” on page 34)
45
55
%
SCLK Frequency
SCLK Duty Cycle
LRCK Edge to SDOUT MSB Output Delay
SDOUT Setup Time Before SCLK Rising Edge
SDOUT Hold Time After SCLK Rising Edge
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
SCLK=MCLK mode 1/t_P
-
MCLK=12.0000 MHz 1/t_P
-
all other modes 1/t_P
-
45
t_d(MSB)
-
t_s(SDO-SK)
20
t_h(SK-SDO)
30
t_s(SD-SK)
20
t_h
20
12.0000
68•F_s
64•F_s
55
52
-
-
-
-
MHz
Hz
Hz
%
ns
ns
ns
ns
ns
14. After powering up the CS42L52, RESET should be held low after the power supplies and clocks are
settled.
15. See “Example System Clock Frequencies” on page 77 for typical MCLK frequencies.
LRCK
SCLK
SDOUT
SDIN
t_s(LK-SK)
t_d(MSB)
t_s(SD-SK)
//
//
t_P
//
//
t_h(SK-SDO)
//
MSB
//
// ^th
MSB
//
t_s(SDO-SK)
MSB-1
MSB-1
Figure 3. Serial Audio Interface Timing
DS680A1
21