CS42L52 Datasheet, PDF (36/82 Pages) Cirrus Logic – Low Power, Stereo CODEC w/Headphone & Speaker Amps

CS42L52
4.7 Digital Interface Formats
The serial port operates in standard I²S, Left-Justified, Right-Justified (DAC only), or DSP Mode digital in-
terface formats with varying bit depths from 16 to 24. Data is clocked out of the ADC or into the DAC on the
rising edge of SCLK.
LRCK
SCLK
Left Channel
Right Channel
SDIN
SDOUT
MSB
AOUTA / AINxA
LSB
MSB
AOUTB / AINxB
LSB
Figure 16. I²S Format
MSB
LRCK
SCLK
SDIN
SDOUT
MSB
Left Channel
Right Channel
AOUTA / AINxA
LSB
MSB
AOUTB / AINxB
Figure 17. Left-Justified Format
LSB
MSB
LRCK
SCLK
SDIN
Left C ha nnel
Right C han nel
MSB
LSB
MSB
AOUTL
Audio Word Length (AWL)
Figure 18. Right-Justified Format (DAC only)
AOUTR
LS B
4.7.1
DSP Mode
In DSP Mode, the LRCK acts as a frame sync for 2 data-packed words (left and right channel) input on
SDIN and output on SDOUT. The MSB is input/output on the first SCLK rising edge after the frame sync
rising edge. The right channel immediately follows the left channel.
LRCK
SCLK
SDIN
1/fs
L SB MSB
Left Channel
LSB MSB
HP/LINE OUTA
Audio Word Length (AWL)
Figure 19. DSP Mode Format)
Right Channel
HP/LINE OUTB
LSB MSB
4.8 Initialization
The CODEC enters a Power-Down state upon initial power-up. The interpolation and decimation filters, del-
ta-sigma and PWM modulators and control port registers are reset. The internal voltage reference, and
switched-capacitor low-pass filters are powered down.
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