CS42L52 Datasheet, PDF (16/82 Pages) Cirrus Logic – Low Power, Stereo CODEC w/Headphone & Speaker Amps

CS42L52
ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ)
(Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; VL = VD = VHP = 1.8 V;
T_A = -40 to +85°C; Measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz and 96 kHz; test load R_L = 10 kΩ,
C_L = 10 pF for the line output (see Figure 2), and test load R_L = 16 Ω, C_L = 10 pF (see Figure 2) for the headphone output.
HPGAIN[2:0] = 011.)
VA = 2.37 - 2.5 V
VA = 1.65 - 1.89 V
Parameters (Note 6)
R_L = 10 kΩ
Dynamic Range
18 to 24-Bit
16-Bit
Total Harmonic Distortion + Noise
18 to 24-Bit
16-Bit
R_L = 16 Ω
Dynamic Range
Min Typ Max Min Typ Max Unit
A-weighted 90
98
-
87
95
-
dB
unweighted 87
95
-
84
92
-
dB
A-weighted -
96
-
-
93
-
dB
unweighted -
93
-
-
90
-
dB
0 dB -
-86
-78
-
-88
-80
dB
-20 dB -
-75
-
-
-72
-
dB
-60 dB -
-35
-27
-
-32
-24
dB
0 dB -
-86
-
-
-88
-
dB
-20 dB -
-73
-
-
-70
-
dB
-60 dB -
-33
-
-
-30
-
dB
18 to 24-Bit
16-Bit
A-weighted 90
98
-
87
95
-
dB
unweighted 87
95
-
84
92
-
dB
A-weighted -
96
-
-
93
-
dB
unweighted -
93
-
-
90
-
dB
Total Harmonic Distortion + Noise
18 to 24-Bit
0 dB -
-75
-67
-
-75
-67
dB
-20 dB -
-75
-
-
-72
-
dB
-60 dB -
-35
-27
-
-32
-24
dB
16-Bit
0 dB -
-75
-
-
-75
-
dB
-20 dB -
-73
-
-
-70
-
dB
-60 dB -
-33
-
-
-30
-
dB
Other Characteristics for R_L = 16 Ω or 10 kΩ
Output Parameters
Modulation Index (MI) -
0.6787
-
-
0.6787
-
(Note 7)
Analog Gain Multiplier (G)
0.6047
0.6047
Full-scale Output Voltage (2•G•MI•VA)
(Note 7) Refer to the table in “Line Output Voltage Level Charac- Vpp
teristics” on page 18
Full-scale Output Power
(Note 7) Refer to the table in “Headphone Output Power Characteristics” on
page 19
Interchannel Isolation (1 kHz)
16 Ω -
80
-
-
80
-
dB
10 kΩ -
95
-
-
93
-
dB
Speaker Amp to HP Amp Isolation
-
80
-
-
80
-
dB
Interchannel Gain Mismatch
-
0.1
0.25
-
0.1
0.25
dB
Gain Drift
-
±100
-
-
±100
- ppm/°C
AC-Load Resistance (R_L)
(Note 8) 16
-
-
16
-
-
Ω
Load Capacitance (C_L)
(Note 8) -
-
150
-
-
150
pF
8. See Figure 2. R_L and C_L reflect the recommended minimum resistance and maximum capacitance re-
quired for the internal op-amp's stability and signal integrity. In this circuit topology, C_L will effectively
move the band-limiting pole of the amp in the output stage. Increasing this value beyond the recom-
mended 150 pF can cause the internal op-amp to become unstable.
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DS680A1